1. Technical Field
The present invention relates to a field effect transistor and a semiconductor device, and to a method for manufacturing thereof.
2. Related Art
Metal insulator semiconductor field effect transistors (MISFET), which are composed of silicon and polycrystalline silicon employed as materials for semiconductor substrate and gate electrode, respectively, exhibit progressively improved performances by virtue of processing technologies for fine devices, various types of deposition technologies and impurity control technologies. Semiconductor devices having various functions are configured by combining different MISFETs that exhibits different threshold voltage properties. In particular, a considerable improvement in the current drive efficiency is obtained by a scaledown of devices. Besides, a MISFET having an oxide film such as silicon oxide film employed as a gate insulating film is particularly referred to as metal oxide semiconductor field effect transistor (MOSFET).
Prior art literatures related to the present invention include: Japanese Patent Laid-Open No. 2002-93921; Japanese Patent Laid-Open No. 2005-57301; Japanese Patent Laid-Open No. 2005-303261; J. Welser, J. L. Hoyt, and J. F. Gibbons, IEEE Electron Device Letters, Vol. 15, No 3 (1994), p. 100-102, entitled “Electron Mobility Enhancement in Strained-Si N-type Metal-Oxide-Semiconductor Field-Effect Transistors”;
S. Itoh et al., Technical Digest of 2000 International Electron Device Meeting (2000), p. 247-250, entitled “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”;
T. Ghani et al., Technical Digest of 2003 International Electron Device Meeting (2003), p. 978-980, entitled “A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors”; and
H. J. Cho et al., Technical Digest of 2004 International Electron Device Meeting (2004), p. 503-506, entitled “The Effects of TaN Thickness and Strained Substrate on the Performance and PBTI Characteristics of Poly-Si/TaN/HfSiON MOSFETs”.
Nevertheless, a scaledown of devices causes a reduced channel-length of FET, causing a difficulty in controlling an electric current in the channel region by employing a gate voltage (electric charge control). A known solution for such difficulty is an utilization of an increased impurity concentration in the channel region of the semiconductor substrate to thereby improve the controllability. However, such process causes an increased scattering of charged carrier (electronic electron hole) by the presence of impurity, deteriorating the current drive efficiency.